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[VHDL-FPGA-Verilog] verilog_lab_solution

Description: Verilog 实验代码。。。经典的，里面都是完整的项目文件。 ISE环境。-Verilog test code. . . Classic, which is a complete project file. ISE environment.
Platform: | Size: 7292928 | Author: jacklee | Hits:

[VHDL-FPGA-Verilog] verilog1

Description: 用verilog语言编写的6分频分频计数器。分频后用来控制蜂鸣器响，也可以修改代码做成更高分频的计数器。压缩包内也包含此分频器的modelsim仿真文件-Verilog language with 6 frequency divider counter. Frequency and used to control the buzzer sound, you can modify the code to make a higher frequency counter. Compressed package also contains this file divider modelsim simulation
Platform: | Size: 143360 | Author: 广子 | Hits:

[VHDL-FPGA-Verilog] adder_verilog

Description: This file is a four bit adder verilog code. its function is to add. it has other verilog files as we-This file is a four bit adder verilog code. its function is to add. it has other verilog files as well
Platform: | Size: 3072 | Author: Joe | Hits:

[VHDL-FPGA-Verilog] System_Demons

Description: 0.最简单的SystemC程序：hello, world. 1.用SystemC实现D触发器的例子，同时也演示了如何生成VCD波形文件。 2.用SystemC实现同步FIFO的例子。这个FIFO是从同文件夹的fifo.v（verilog代码）翻译过来的。 3.如何在SystemC中实现延时（类似verilog中的#time）的例子。 4.SystemC文档《User Guide》中的例子。注意和文挡中稍有不同的是修改了packet.h文件，重载了=和<<操作符。这其实也演示了在sc_signal中如何使用用户自定义的struct。 5.构造函数带参数的例子。 6.轮转仲裁的例子。 7.使用类摸板的例子。 8.如何在模块中包含子模块。 9.SystemC的Transaction级验证示例。 10.如何trace一个数组 11.SystemC中使用测试向量文件输入的例子。 12.SystemC采用UDP/TCP通信的例子。 13.Cadence的ncsc的例子。 -0 most simple SystemC program: hello, world. A D flip-flop using SystemC example also demonstrates how to generate VCD waveform files. Synchronous FIFO example using SystemC. FIFO is from the same folder fifo.v (Verilog code) translated. Delay (similar to verilog# time). In SystemC examples. 4.SystemC document the "User Guide" in the example. Note the slightly different cultural block is modified the packet.h file, reload = << operator. In fact, this also demonstrates how to use user-defined struct in sc_signal. Constructor with parameters example. (6) examples of web arbitration. 7. The class Moban examples. 8 module contains a sub-module. 9.SystemC of Transaction-Level Verification example. 10 How to trace an array 11.SystemC use the example of the test vector file input. 12.SystemC using the example of the UDP/TCP communication. Examples of 13.Cadence the ncsc.
Platform: | Size: 532480 | Author: sdd | Hits:

[VHDL-FPGA-Verilog] .tranfervw

Description: 一款可以生成.vwf的小软件 对编写verilog语言很有用-a software for vwf file of verilog code programming
Platform: | Size: 1068032 | Author: 贺铮 | Hits:

[VHDL-FPGA-Verilog] poc

Description: verilog 写的POC接口代码。测试波形功能通过。内有波形模拟CPU以及仿真文件。-A poc module written by verilogHDL.Can be used in communicating with MCUs. The simulate wave file is already inside.
Platform: | Size: 220160 | Author: 王润 | Hits:

[VHDL-FPGA-Verilog] linux

Description: 在硬件电路的设计中，会产生大量的Verilog HDL代码，由于这些代码是自动生成的，其文件名没有实际意义，代码没有注释，也没有相关的说明文档，给阅读和理解带来了不便-In the hardware circuit design, will produce a large number of Verilog HDL code, the code is automatically generated, the file name of no practical significance, code no comments, no relevant documentation, to read and understand the inconvenience
Platform: | Size: 46080 | Author: 朱鹏 | Hits:

[VHDL-FPGA-Verilog] Bit_synchronization

Description: 这是一个位同步的FPGA完整代码，是用Verilog写的，其中包括分频、时钟、时钟提取等各模块以及顶层文件，做调制解调的朋友可以-This is a synchronous FPGA complete code is written in Verilog, including frequency, clock, clock extraction module and the top-level file, do the modulation and demodulation of a friend can see.
Platform: | Size: 3072 | Author: | Hits:

[VHDL-FPGA-Verilog] gray

Description: verilog语言编写的十分频器源码和测试文件-a program of ten divider,with a source and test file,using the verilog language
Platform: | Size: 1024 | Author: Princess | Hits:

[VHDL-FPGA-Verilog] Clk_5

Description: 本文件为verilog所描述的基数分频技术，此实例为5分频电路。-This file is the verilog described base sub-band technology, this instance as a divider circuit.
Platform: | Size: 248832 | Author: 王刚 | Hits:

[VHDL-FPGA-Verilog] VGA_CCD531

Description: 本文围绕一个包含Nios II软核处理器的可编程片上系统展开数码相机的样机设计。论文首先对样机所要达到的整体功能进行了规划，接下来并行开展了软硬件设计。在硬件方面，充分利用了所使用平台提供的SD卡插槽、键盘、数码管、SRAM等各种硬件资源，并用Verilog HDL硬件描述语言设计了样机系统所需要的VGA接口控制器、CMOS图像传感器接口控制器以及VGA显示存储器；在软件方面，本文基于Nios II软核处理器用C语言实现了SD卡的驱动、FAT文件系统的移植、VGA显视器的驱动以及BMP图片文件的转换与显示等功能，并能通过键盘操作和用户界面控制样机拍照和相片浏览。实验结果表明本样机系统设计正确，软硬件各模块绝大部分工作正常，为进一步研究数码相机的应用建立起了一个实用平台。-This paper focuses on a Nios II soft core processors, programmable on-chip system to launch a digital camera prototype design. Firstly, the overall function of the prototype to be achieved by planning, then in parallel hardware and software design. Take full advantage of the hardware side, using the platform provided by the SD card slot, keyboard, digital tube, SRAM and other hardware resources, and using Verilog HDL hardware description language to design a prototype system VGA interface controller, CMOS image sensors interface controller and the VGA display memory the software side, based on the Nios II soft core processor implemented in C, the SD card driver, and the transplantation of the FAT file system, the VGA display driver, and BMP image file conversion and display function, and through the keyboard and user interface control prototype photographs and photo browsing. The experimental results show that this prototype system is designed properly, most of the hardware and softwa
Platform: | Size: 15078400 | Author: | Hits:

[VHDL-FPGA-Verilog] RISC-CPU

Description: 用FPGA实现一个简易的CPU，采用精简指令集结构，每一条指令有16bit，高三位为指令操作数，后13位为地址，该CPU能实现8种指令操作，分别有HLT（空一个中期）ADD（相加操作）SKZ（为零跳过）AND（相与操作）XOR（异或操作）LDA（读数据）STO（写数据）JMP（无条件跳转指令）。cpu包括8个部件，分别为时钟发生器、指令寄存器、累加器、算术逻辑单元、数据控制器、状态控制器、程序计数器、地址多路器，各个部件之间的相互操作关系由状态控制器来控制，程序指令存放在初始rom中，本例程存放在存储器初始文件中。 PS：为什么没有Verilog选项呢-A simple CPU, FPGA implementation to streamline the instruction set architecture, each instruction 16bit, high three operands for the instruction, the 13 address, the CPU can achieve the eight kinds of instruction operations, respectively, HLT (a medium-term empty) ADD (add operation) SKZ (zero skip) AND (phase operation) the XOR (exclusive OR operation) LDA (read data) STO (write data) JMP (unconditional jump instruction). cpu consists of eight parts, clock generator, the instruction register, accumulator, arithmetic logic unit, the data controller, the state controller, the program counter, the address multiplexer, the various components interoperate relations by the state controller to control, program instructions stored in the initial rom the routines stored in memory the initial file. PS: Why is there no Verilog options.
Platform: | Size: 3147776 | Author: vice | Hits:

[VHDL-FPGA-Verilog] FA161_LCD_display

Description: 联华众科FA161的开发板上实现LCD显示的一个工程文件，编程语言Verilog。可以在LCD上显示按键值。-Lianhua Zhongke FA161 development board LCD display, a project file, programming languages ​ ​ Verilog. The key values ​ ​ can be displayed on the LCD.
Platform: | Size: 535552 | Author: 冬瓜 | Hits:

[Other] counter

Description: there is a text file of code for 8 bit up counter in verilog.
Platform: | Size: 1024 | Author: amit | Hits:

[VHDL-FPGA-Verilog] a1

Description: 1 bit MUX 用ISE写的1bit MUX的verilog code 可以在ISE上模拟1bit MUX的运作-1 bit MUX It is a file of verilog code to design a 1 bit MUX. It is design by ISEbit
Platform: | Size: 1024 | Author: 崔博 | Hits:

[VHDL-FPGA-Verilog] DE2_70_NIOS_10_flash

Description: 首先将此Verilog程序下载到DE2-70开发板上后，然后用NiosII软件将任何文件的二进制数据写入到ssram或者sdram等存储器重去，并可以指定起始地址。-First program this Verilog downloaded to the DE2-70 development board, and then the use NiosII software binary data of any file written to memory such as ssram or sdram weight go, and you can specify a starting address.
Platform: | Size: 1620992 | Author: boyzone | Hits:

[VHDL-FPGA-Verilog] ldpc-encode

Description: 深空通信中AR4JA码编码的研究与实现，ＡＲ４ＪＡ码是ＬＤＰＣ码的一种，文件中是Ｖｅｒｉｌｏｇ语言的硬件实现。-Research and Implementation of the Deep Space Communications AR4JA coding, AR4JA code LDPC codes a hardware implementation of the Verilog language file.
Platform: | Size: 3565568 | Author: liangliang | Hits:

[VHDL-FPGA-Verilog] ad7928

Description: ad7928的采集控制，用verilog HDL语言编写，已在测试板上测试程序。-Ad7928 collection control, use verilog HDL language, and has set up a file in the test board test procedure.
Platform: | Size: 1024 | Author: 金伟 | Hits:

[VHDL-FPGA-Verilog] ad7938

Description: AD7938控制程序，用VERILOG HDL语言编写，已在平台测试。-AD7938 control procedures, the use of VERILOG HDL language, and has set up a file in the platform test.
Platform: | Size: 3072 | Author: 金伟 | Hits:

[Other] Desktop

Description: 实现一个32位高精度的filter输出，内含.v文件，使用verilog-A 32-bit high-precision filter output, containing v file using verilog
Platform: | Size: 83968 | Author: 吴九鹏 | Hits:
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